Computing has evolved from being a luxury to an essential part of our daily lives. With the rise of applications like machine learning and 5G mobile networks, there is an increasing demand for high computing performance. This shift has led to the development of more energy-efficient and cost-effective systems such as “chiplets” to ensure these applications run seamlessly.
Chiplets are unpackaged dies that can be grouped together in a package with other chiplets within a single chip. Each chiplet is designed to perform a specific function, and there are various approaches to integrating chiplets. The fundamental idea is to have a library of chiplets that can be assembled in a package and interconnected using a die-to-die interconnect scheme.
In response to the increasing complexity and challenges posed by on-package routing density and data rates in high-speed interchiplet serial links, a team led by Jingtong Hu at the University of Pittsburgh has developed SPIRAL. This framework enables signal-power integrity co-analysis of interchiplet serial links, offering a more efficient way to design and validate chiplet-based systems.
SPIRAL leverages machine-learning based transmitter models and impulse response based models for channels and receivers to build equivalent models for the interchiplet links. By co-analyzing signal and power integrity using pulse response methods, SPIRAL addresses the limitations of existing tools like SPICE, which have struggled to accurately analyze and validate chiplet technology due to its novelty.
Chiplets represent a significant advancement in the field of computing, enabling higher performance, energy efficiency, and cost-effectiveness in systems that utilize them. The development of tools like SPIRAL is crucial in ensuring the successful implementation of chiplet-based designs, paving the way for a more efficient and robust computing future.
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